AMD 上海研发中心招聘 ASIC design verification engineer

aftyingjiesheng

AMD 上海研发中心招聘 ASIC design verification engineer


1 }. x  X. m, U职位要求:
  `% @1 I, N* L, S+ T4 f1 N$ n$ c
; `3 }! e7 U3 w' ^; u
# I" n6 B/ k/ u! j+ p2 v7 NAMD 上海研发中心招聘 ASIC design verification engineer

3 z1 `# D/ S( n7 z4 WMTS/Sr. ASIC Engineer:
9 L  z9 G# G, J" U9 L4 |  
      
9 X$ a2 M! a! `6 g! O$ |Position Summary
6 Q5 u$ N# D0 A/ K$ q+ j
- Participate IP and SoC level architecture definition, derive functional and design specifications and analyze feasibility of technical and architectures.
# \. s) J8 s+ x
; L9 J9 `6 D! l2 I- Implement design with Verilog to achieve specification goals. Simulate and debug the codes in coding stage.
" t+ G" P- V- M0 W6 z$ ^
- Go through the FE design flow to deliver qualified netlist. Feedback to Physical Design team to help to close timing and check floorplan.
# {1 ?! i+ F$ o" z7 u
- Write ASIC specific part of test plan. Prove functional correctness from block level to SoC level
/ e9 c( E+ h+ ]6 ?0 b
- Support FW/SW bring-up and debugging

# O# b  }! M; W( @, Y- Working as the technical point of contact on the ASIC area.
& b$ z! B1 M1 p7 J
- Maintain design environment, solve flow issues, and develop scripts to improve flow efficiency.

7 k) O, G: @$ i+ S& W% t
Essential Functions:

6 c" a8 J9 k7 ?( d' s8 XRTL, Verification, Testbench, SystemC, SystemVerilog, OVM

Essential Requirements/Qualifications:

- Proven ASIC / SoC Design / Verification Experience

5 b7 ~3 K! S( Y( P- m' Z- Must have strong background on IP development


) [! F# N9 b$ M6 i1 d0 D7 MDesired:

+ M1 l: j! k3 S2 n- Major in EE & CS
2 O0 o  o! c' s# C3 I. |
- Must be proficient in Verilog coding, debugging and modeling
1 A& u: r( N3 }* y5 W9 q* W: q
' P, o) q: G: d$ u. W* R- Should be familiar with Advanced C/C++/SystemVerilog, RTL coding techniques.

- PCIe, BIOS, ACPI experience would be an asset.

. S0 x6 p' Z( x6 c6 u) Q. Z- Must be familiar with Design for verification Methodology (assertion based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.)

- Should be familiar with ASIC design flow, such as synthesis, DFT, timing analysis, ECO etc.
4 s  p5 p" V9 G: n8 j
: z4 ^. \) [4 C7 s! |6 t- Must be familiar with shell/perl/tcl programming in linux OS.
% e' n' H4 I3 e8 T+ M
- Should have strong problem solving skills

' X( G2 e5 s" A! N- P' _( d/ F- Good English hearing, speaking, reading and writing capabilities.
1 y* {5 ?& x1 A5 j4 d- P
" V5 b1 N. q6 l1 {% ~2 m' M7 {+ K- Good communication skills
2 R2 g, ~7 b( R8 o
7 P% t; u0 j$ R9 I5 I# f" l! X- Will be a big plus if having mass production tape‐out experience.
# J5 e$ q+ O7 L+ t- O" b# W
在线简历投递：http://bbs.aftjob.com/thread-608678-1-1.html
1 G  g, V% R) E, \' }7 PAMD求职俱乐部：http://bbs.aftjob.com/group-60-1.html
4 A/ M6 j) }2 M6 C# l
8 u6 i7 r" M2 E4 l' t
& _+ F0 t9 n" m; ^5 \" j