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[招聘] AMD 上海研发中心招聘 ASIC design verification engineer

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发表于 2011-6-20 12:26 | 显示全部楼层 |阅读模式
AMD 上海研发中心招聘 ASIC design verification engineer6 g5 K' }" `/ M. [1 l8 c% q
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! k* h! Y- D; J9 w职位要求:4 O" F4 h  q, b2 ~* ~3 e! q

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AMD 上海研发中心招聘 ASIC design verification engineer
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MTS/Sr. ASIC Engineer:1 z& ]# k6 [4 v
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Position Summary" A* v7 I, U# k. Y% c& \2 `) G

% h+ X9 H+ e* b+ u( q5 ^, {$ v- Participate IP and SoC level architecture definition, derive functional and design specifications and analyze feasibility of technical and architectures.# W( X4 @) @! Z! e

  z4 Z5 V) k% f0 R6 j2 V- Implement design with Verilog to achieve specification goals. Simulate and debug the codes in coding stage.
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- Go through the FE design flow to deliver qualified netlist. Feedback to Physical Design team to help to close timing and check floorplan.7 k' G6 U7 I0 Q( E9 o& i, Q6 @( J

  o' d% `9 O! T& {9 B) Y- Write ASIC specific part of test plan. Prove functional correctness from block level to SoC level- z6 s; D& i% g+ D, {
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- Support FW/SW bring-up and debugging# k6 T# V+ W2 {0 S6 ^) k
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- Working as the technical point of contact on the ASIC area.
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0 [, z* Y+ x. N. D4 {8 t- Maintain design environment, solve flow issues, and develop scripts to improve flow efficiency.
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Essential Functions:4 a3 @5 k9 U* ]3 x

* r) h4 T7 h, H! URTL, Verification, Testbench, SystemC, SystemVerilog, OVM
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Essential Requirements/Qualifications:# @8 m6 P1 E  D+ K: N, R) g, B
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- Proven ASIC / SoC Design / Verification Experience
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- Must have strong background on IP development4 `" ]) h/ n7 d0 R* c$ @
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' ~: f) K( C/ j8 U- Z4 FDesired:
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/ o  b9 P6 D) |  J; h" V- Major in EE & CS+ D# e9 e8 L/ X: V8 @3 |

0 q! L0 \6 r# ~, S6 \3 K7 [. k. r) Q- Must be proficient in Verilog coding, debugging and modeling
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- Should be familiar with Advanced C/C++/SystemVerilog, RTL coding techniques.
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7 t8 T& Q7 V6 v$ [1 c- PCIe, BIOS, ACPI experience would be an asset.
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- Must be familiar with Design for verification Methodology (assertion based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.). u6 _( l$ j5 g) u# k- C# r
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- Should be familiar with ASIC design flow, such as synthesis, DFT, timing analysis, ECO etc.' |$ S3 j! l' k/ P2 A, Y
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- Must be familiar with shell/perl/tcl programming in linux OS.7 i. j: j# K7 E

' D" R9 y5 Z5 e, a6 S6 f! S- Should have strong problem solving skills& {2 d( U, U1 \- L. V& D
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- Good English hearing, speaking, reading and writing capabilities.
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- Good communication skills. H0 k" {% Q/ W+ p' A1 \* _

0 Y4 X+ v( |" t3 F. R- Will be a big plus if having mass production tape‐out experience.6 l( \) L. i- w! |- m; }! ^

$ R# s% @- u) q8 y! Y  Y" \! t/ V在线简历投递:http://bbs.aftjob.com/thread-608678-1-1.html
' K/ ~: W0 [+ ]  X! aAMD求职俱乐部:http://bbs.aftjob.com/group-60-1.html
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