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[招聘] AMD 上海研发中心招聘 ASIC design verification engineer

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发表于 2011-6-20 12:26 | 显示全部楼层 |阅读模式
AMD 上海研发中心招聘 ASIC design verification engineer  `5 ~9 _& F/ x6 B7 _- \
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职位要求:( }5 y' C; t6 V+ y; v- B

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% ~0 y, j/ f( D* YAMD 上海研发中心招聘 ASIC design verification engineer) ^5 c$ K& x7 z/ [

) |! K- `! m( N0 r* R5 iMTS/Sr. ASIC Engineer:
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5 }) h$ X+ O* D, d$ i2 wPosition Summary& q% C, A4 r( z  k
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- Participate IP and SoC level architecture definition, derive functional and design specifications and analyze feasibility of technical and architectures.
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- Implement design with Verilog to achieve specification goals. Simulate and debug the codes in coding stage.6 a" ~; R* {! \# }. o% Y+ h, w* @
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- Go through the FE design flow to deliver qualified netlist. Feedback to Physical Design team to help to close timing and check floorplan.) {5 F4 }8 ?: F' G4 ^1 @, e; H( A
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- Write ASIC specific part of test plan. Prove functional correctness from block level to SoC level- s% D9 z& u* [* v$ R0 W

2 ~/ F8 o- ^# L: }- U- Support FW/SW bring-up and debugging
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9 E7 l. {4 Y: r" `3 K% Z+ E8 F- Working as the technical point of contact on the ASIC area.- u! \  B# F( b4 @9 n1 ]* M
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- Maintain design environment, solve flow issues, and develop scripts to improve flow efficiency.
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8 `" |! z2 X' G  y4 v" oEssential Functions:
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9 P  k% q$ {7 X! @! e& x7 i0 F+ U4 gRTL, Verification, Testbench, SystemC, SystemVerilog, OVM. B. E/ A/ }3 `* `" x
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Essential Requirements/Qualifications:
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- Proven ASIC / SoC Design / Verification Experience4 p* S5 T: y- @( j$ k

' R; T( a. o0 A9 N7 F4 J0 N- Must have strong background on IP development7 {& I! m3 Z5 Z6 X
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Desired:  X! y7 }0 F# L: \2 n. D, L
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- Major in EE & CS
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- Must be proficient in Verilog coding, debugging and modeling$ e  K! X! q/ S9 ?" F+ K' W

4 C6 O; }$ h; v1 m- Should be familiar with Advanced C/C++/SystemVerilog, RTL coding techniques.3 G% t9 R% w. |; O* z% a/ P+ Z# ]6 j

" @$ G/ h& j  z; _- PCIe, BIOS, ACPI experience would be an asset.* F0 O9 V- [! T; g6 r" F+ H
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- Must be familiar with Design for verification Methodology (assertion based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.)
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9 T: S) L( Z" N- Should be familiar with ASIC design flow, such as synthesis, DFT, timing analysis, ECO etc./ A# C4 }6 Z/ v4 m# Q+ d) N

5 A( `1 ^5 J1 e, E5 q' J8 w! t: s) y- Must be familiar with shell/perl/tcl programming in linux OS.
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0 T4 ?( f! V- m" n) D- Should have strong problem solving skills
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* y3 Z4 C- t' V2 }; X- Good English hearing, speaking, reading and writing capabilities.
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- Good communication skills7 J, q8 Q  L, u* v$ \4 K  ~
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- Will be a big plus if having mass production tape‐out experience.1 N4 X( G1 v- N7 ?2 m  g" {7 o

- d" M  N7 h  k* p9 D# y) y8 R, ^) p  F在线简历投递:http://bbs.aftjob.com/thread-608678-1-1.html
; i9 t2 m. G, \AMD求职俱乐部:http://bbs.aftjob.com/group-60-1.html
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