找回密码
 加入后院

QQ登录

只需一步,快速开始

搜索
查看: 726|回复: 0

[招聘] AMD 上海研发中心招聘 ASIC design verification engineer

[复制链接]
发表于 2011-6-30 10:27 | 显示全部楼层 |阅读模式
AMD 上海研发中心招聘 ASIC design verification engineer
+ O( f, Y( p2 }2 |9 k( h( S6 R: C2 V" U! k' w% m1 q' M* @

  i1 z: P, Q% ~  i$ PMTS/Sr. ASIC Engineer:
- _5 `" j6 Y8 ^2 P+ H6 L3 |' F  ( U- p& V3 H$ }3 ?" L' ^
      
! e1 J% U5 w( x) b9 VPosition Summary6 a% N- l, h  K6 V4 T2 J
* d; S  w/ i0 a3 C
- Participate IP and SoC level architecture definition, derive functional and design specifications and analyze feasibility of technical and architectures.
; o: K) A7 |7 k% K; b4 T4 A! M
; o* |. w; }; f3 @4 Q; u9 g9 d) T! d: P- Implement design with Verilog to achieve specification goals. Simulate and debug the codes in coding stage.
  c1 X/ Z, e# u' c7 F* s8 L4 z( j* S" [) d* W
- Go through the FE design flow to deliver qualified netlist. Feedback to Physical Design team to help to close timing and check floorplan.) ^3 T2 ?( ~* r1 x) `

: W# O( [1 ^  q0 T# S0 M# \- Write ASIC specific part of test plan. Prove functional correctness from block level to SoC level
8 w. W7 X5 Y  y
& c& i1 T) W( Y1 a- Support FW/SW bring-up and debugging
. T9 w  g6 c) V2 c' Z' g" G; I& U1 X1 G2 S2 r" j* K! m& A; F+ h: T
- Working as the technical point of contact on the ASIC area.
  c) i: d$ b& A: g: E! U, E9 k" y4 ]2 _, U& c- w
- Maintain design environment, solve flow issues, and develop scripts to improve flow efficiency.
. g5 j' Q1 v6 O$ }% ~8 r# S! a! b
6 {  B. j& I" n. W! b
Essential Functions:% T+ X4 Q/ A) j$ d

" w. B+ d! b1 ~8 N# r- V: ^* T% @RTL, Verification, Testbench, SystemC, SystemVerilog, OVM1 G: M# h2 A. `2 ]" {, @2 ]$ Z

" ?2 G2 a3 [7 c7 K. O' OEssential Requirements/Qualifications:" H3 K# Z- s3 Z

/ k3 s& }: j' z% {5 i' C0 A# K- Proven ASIC / SoC Design / Verification Experience% k' l% T, B" {2 a! A

, D+ W8 z9 j' ~- Must have strong background on IP development
3 \. m' [. {6 `( d4 M- j5 l$ _/ G2 d
1 ]' E2 x# ^  N& H( X+ N; |) S# A' q% a
Desired:5 t; l( J* X0 n5 [9 A
# J. z* l7 L  w* G2 {2 o7 R1 K' e
- Major in EE & CS  \7 U. G$ L0 }# c+ r9 W8 O6 J
7 A' j0 T9 o0 I* i: ]
- Must be proficient in Verilog coding, debugging and modeling) N- c+ H# O6 S% B# C$ m& g9 P+ S( E

+ E4 i( P# z/ Z- Should be familiar with Advanced C/C++/SystemVerilog, RTL coding techniques.
( ?1 V- q; F( k; m0 b- N( `4 b2 B% a. D* d7 L! S+ A
- PCIe, BIOS, ACPI experience would be an asset.
! m5 k: q8 r: [. o8 L, n- n9 X. U2 F" ]+ x" u1 [* C
- Must be familiar with Design for verification Methodology (assertion based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.)
9 d1 y" H+ V# a
/ J) o! z/ P/ e- b# j- Should be familiar with ASIC design flow, such as synthesis, DFT, timing analysis, ECO etc.! J) R% x; A) C/ R$ b) g

' j2 K4 p1 S+ ]6 L2 Z- Must be familiar with shell/perl/tcl programming in linux OS.
9 l* y" z, O! f" P' ?" k7 Y9 `& I2 w, f9 {  @: ]7 @- t' u  G
- Should have strong problem solving skills
; Q+ s1 D, J8 r0 r" r. s( \  z  V* f% W) {
- Good English hearing, speaking, reading and writing capabilities.
2 u7 x' o& }& G6 o) R' x- h* i  z% `7 f" A
- Good communication skills
! O  l3 H1 D- g! i9 y( ?7 [8 ~6 n; b6 Z1 e
- Will be a big plus if having mass production tape‐out experience.
% N8 ~6 l2 g5 e4 k. ~* a3 A+ G: t7 |- X
简历投递:http://bbs.aftjob.com/thread-608678-1-1.html
$ o8 H7 o2 k9 t' Z: z2 U  dAMD求职俱乐部:http://bbs.aftjob.com/group-60-1.html
您需要登录后才可以回帖 登录 | 加入后院

本版积分规则

Archiver|手机版|小黑屋|广告业务Q|工大后院 ( 粤ICP备10013660号 )

GMT+8, 2026-7-29 04:05

Powered by Discuz! X5.0

© 2001-2026 Discuz! Team.

快速回复 返回顶部 返回列表