AMD 上海研发中心招聘 ASIC design verification engineer

aftyingjiesheng

AMD 上海研发中心招聘 ASIC design verification engineer


MTS/Sr. ASIC Engineer:
* Q- K) ^- Q9 g. \  d  
: |' Y# V, D+ p/ @      
Position Summary

3 @- n, P* Y. U- Participate IP and SoC level architecture definition, derive functional and design specifications and analyze feasibility of technical and architectures.

- Implement design with Verilog to achieve specification goals. Simulate and debug the codes in coding stage.

- Go through the FE design flow to deliver qualified netlist. Feedback to Physical Design team to help to close timing and check floorplan.
) K$ j2 e; u/ y3 a  {
  x! a4 j# p/ x0 K- Write ASIC specific part of test plan. Prove functional correctness from block level to SoC level

- Support FW/SW bring-up and debugging
. |& _6 I' [/ B+ B
9 `2 d' @  ?: Q- Working as the technical point of contact on the ASIC area.
5 }9 [+ h" P0 X" U. a- \9 }% f* F
- Maintain design environment, solve flow issues, and develop scripts to improve flow efficiency.


: t6 f8 p; N+ C0 D2 q8 o) EEssential Functions:
1 D5 `; w1 h& M) I7 R
& C3 @; S- |/ h( P* v9 S$ jRTL, Verification, Testbench, SystemC, SystemVerilog, OVM
0 [$ W% Y: A; O: r6 I) @
; H7 `4 v' h3 EEssential Requirements/Qualifications:

- Proven ASIC / SoC Design / Verification Experience

: |8 n* c; p' F: k7 M6 N5 s" k- Must have strong background on IP development
: E7 @+ s/ R- J1 D: K& m

Desired:

- Major in EE & CS

* R+ S' G! f. R, p8 H: m* d- Must be proficient in Verilog coding, debugging and modeling
) V4 c/ ^- H+ l1 C; S
6 I7 N, J; G/ i1 H$ q/ t- Should be familiar with Advanced C/C++/SystemVerilog, RTL coding techniques.
$ s9 _: {! K& ~# f/ v% X
9 w) s6 i4 t7 l- PCIe, BIOS, ACPI experience would be an asset.
; S& l+ I9 |" S8 k
- o" u- B2 W4 _$ B* r+ K+ N* ^$ p- Must be familiar with Design for verification Methodology (assertion based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.)
8 _% d- Z  |. z
- Should be familiar with ASIC design flow, such as synthesis, DFT, timing analysis, ECO etc.

& G1 r: M3 f) {- Must be familiar with shell/perl/tcl programming in linux OS.
6 g. D% M* ]0 {0 ]! L9 E$ c+ e. {1 b
- Should have strong problem solving skills
" K8 A: i. [' [0 I0 s7 H
- Good English hearing, speaking, reading and writing capabilities.

% O6 I7 B( U5 v- {# ]' [+ d- Good communication skills
1 u4 u' q( C4 Z3 [3 |- @- K
5 T0 T: }' c: n- s- Will be a big plus if having mass production tape‐out experience.
7 p8 {- Q$ W5 g* E
1 X2 n7 e" `2 @+ x' `* v简历投递：http://bbs.aftjob.com/thread-608678-1-1.html
+ c& H4 d7 M  b# l' [3 BAMD求职俱乐部：http://bbs.aftjob.com/group-60-1.html