AMD 上海研发中心招聘 ASIC design verification engineer

aftyingjiesheng

AMD 上海研发中心招聘 ASIC design verification engineer
) R; x6 I2 _" U

MTS/Sr. ASIC Engineer:
  
" _" R( s7 e1 V$ {! f      
. Z9 ^# \3 h' j4 \Position Summary
" ~3 A: C  P( s0 _+ P
6 \) w8 p. r3 F5 ~  w2 ~4 X- Participate IP and SoC level architecture definition, derive functional and design specifications and analyze feasibility of technical and architectures.

- Implement design with Verilog to achieve specification goals. Simulate and debug the codes in coding stage.

- Go through the FE design flow to deliver qualified netlist. Feedback to Physical Design team to help to close timing and check floorplan.

6 s0 d" ~  L5 ^% ]/ I- Write ASIC specific part of test plan. Prove functional correctness from block level to SoC level
( _6 k4 f; f& p3 i7 |
9 m' B) `% @/ @4 Z- Support FW/SW bring-up and debugging
. h0 r2 R4 q2 I" \8 m7 l! |- m
  ?& I3 V  G( x2 x/ E/ \/ x$ ^, L' ]9 h- Working as the technical point of contact on the ASIC area.
! F4 K9 S! X% c/ C9 T! ?# s
- Maintain design environment, solve flow issues, and develop scripts to improve flow efficiency.
9 Z6 u0 c* q7 n6 D

  u  y' ^* F& s: P% g0 ]0 V( REssential Functions:

RTL, Verification, Testbench, SystemC, SystemVerilog, OVM
* p; f3 f4 j6 |
7 e: H/ Y& _% R/ L/ v( ZEssential Requirements/Qualifications:

, F4 Z0 c, V/ W+ ~$ Y5 B- Proven ASIC / SoC Design / Verification Experience
( z; _  v0 X1 Q+ J; h3 m
; D- u  {8 E9 `' ]4 V! f5 B' \; p- Must have strong background on IP development

4 S  c3 N" H6 f- L% W: Z
: ~7 n2 F! {% |# JDesired:

- Major in EE & CS
9 ^: w  |6 |$ k
- Must be proficient in Verilog coding, debugging and modeling
; H. P; b! k# n& p
- P: d  E! U+ c- Should be familiar with Advanced C/C++/SystemVerilog, RTL coding techniques.
2 m9 ?# m% \$ H" q! Q( J
0 ]. n3 ~+ k9 V& H0 G- PCIe, BIOS, ACPI experience would be an asset.
$ f* r5 z  E$ F% Y
- Must be familiar with Design for verification Methodology (assertion based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.)

) b+ q4 x! z) H5 B- J: ?- Should be familiar with ASIC design flow, such as synthesis, DFT, timing analysis, ECO etc.
9 L8 Z0 B5 W) Z/ @
, |0 t# b) B1 s9 }* V7 A- Must be familiar with shell/perl/tcl programming in linux OS.
- _, w; {$ k: [) L1 D( {& A( l; i: i' ~  r
- Should have strong problem solving skills

( ]* U: R3 T5 k& s4 J- Good English hearing, speaking, reading and writing capabilities.
/ f9 y8 }: T; e" K
9 V. E( ?- @' [' o- Good communication skills
6 ]- D$ t# t  F/ J. a
8 S3 h( v6 X6 {; Z" n& ^) r- Will be a big plus if having mass production tape‐out experience.

( _+ m* b( z9 y5 a) p9 [# y简历投递：http://bbs.aftjob.com/thread-608678-1-1.html
AMD求职俱乐部：http://bbs.aftjob.com/group-60-1.html